Vlsi Circuits And Systems Group
 
 

 

Conference Papers

2015 2014 2013 2012 2011 2010 2009 2008 2007 2006 2005 2004 2003 2002 2001 2000 1999 1998 1997 1996 1995 1994 1993 1992

2015

  • U. Ruhrmair, J. Hurtado, X. Xu, C. Kraeh, C. Hilgers, D. Kononchuk, J. Finley, W.Burleson. Virtual Proofs of Reality and Their Physical Implementation. IEEE Symposium on Security and Privacy, 2015.

2014

  • U. Ruhrmair*, X. Xu*, J. Solter, A. Mahmoud, M. Majzoobi, F. Koushanfar, and W. Burleson. Efficient power and timing side channels for physical unclonable functions. Cryptographic Hardware and Embedded Systems-CHES, 2014.(*equally contributing authors)

  • V. Suresh and W. Burleson, REFLEX: Re-configurable Logic for Entropy Extraction, at IEEE System on Chip Conference, SOCC 2014, Las Vegas, NV, USA, Sep 3-5, 2014

  • R. Kumar, P. Jovanovic, W. Burleson and I. Polian, Parametric Trojans for Fault-based Attacks on Cryptographic Hardware, at Fault Diagnostics and Tolerance in Cryptography, FDTC 2014

  • X. Xu, V. Suresh, R. Kumar and W. Burleson, Post-Silicon Validation and Calibration of Hardware Security Primitives, at IEEE Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, June 9-11 2014

  • V. Suresh and W. Burleson, Variation Aware Design of Post-Silicon Tunable Clock Buffer, at IEEE Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, June 9-11 2014

  • R. Kumar and W. Burleson, On Design of a Highly Secure PUF based on Non-linear Current Mirrors, at IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2014, Arlington, VA, USA, May 6-7, 2014 IEEE

  • X. Xu, and W. Burleson. Hybrid side-channel/machine-learning attacks on PUFs: a new threat?., Proceedings of the conference on Design, Automation & Test in Europe. DATE, 2014.

  • V. Suresh and W. Burleson, Fine Grained Wearout Sensing using Metastability resolution Time, at ISQED 2014, Santa Clara, CA, USA, March 10-12 2014 IEEE

  • M. Buckler and W. Burleson, Predictive Synchronization for DVFS-Enabled Multi-Processor Systems, at ISQED 2014, Santa Clara, CA, USA, March 10-12 2014 pdf

2013

  • M. Buckler, W. Burleson, G. Sadowski, Low-power Networks-on-Chip: Progress and remaining challenges, IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013, Beijing, China, Sept 4-6, 2013 IEEE

  • R. Kumar and W. Burleson, Litho-aware and Low Power Design of a Secure Current-based Physically Unclonable Function, IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013, Beijing, China, Sept 4-6, 2013 IEEE

  • G. T. Becker, F. Regazzoni, C. Paar and W. Burleson, Stealthy Dopant-Level Hardware Trojans, Workshop on Cryptographic Hardware and Embedded Systems, CHES 2013, Santa Barbara, USA, August 20-23, 2013 pdf

  • G. Hinterwälder, C. T. Zenger, F. Baldimtsi, A. Lysyanskaya, C. Paar, W. P. Burleson Efficient E-cash in Practice: NFC-based Payments for Public Transportation Systems To appear at 13th Privacy Enhancing Technologies Symposium (PETS 2013), Bloomington, USA pdf

  • V. Suresh, D. Antonioli and W. Burleson, On-chip Lightweight Implementation of Reduced NIST Randomness Test Suite at IEEE Intl. Symposium on Hardware-Oriented Security and Trust, HOST 2013

  • A. Rupp, G. Hinterwälder, F. Baldimtsi, C. Paar, P4R: Privacy-Preserving Pre-Payments with Refunds for Tranportation Systems In Fincancial Cryptography and Data Security 2013 (FC 2013), Okinawa, Japan pdf

  • V. C. Patil, S. Srinivasan, W. P. Burlseon, S. Kundu, Impact of Clock-Gating on Power Distribution Network using Wavelet Analysis 26th International Conference on VLSI Design (VLSID), Pune, India, 2013 pdf

2012

  • G. Hinterwälder, C. Paar, and W. P. Burleson, Privacy Preserving Payments on Computational RFID Devices with Application in Intelligent Transportation Systems, in 8TH Workshop on RFID Security and Privacy (RFIDSec 2012), Nijmegen, Netherlands 2012 pdf

  • F. Baldimtsi, G. Hinterwälder, A. Rupp, A. Lysyanskaya, C. Paar and W. P. Burleson, Pay as you Go, Workshop on Hot Topics in Privacy Enhancing Technologies, Vigo, Spain, 2012 pdf

  • V. Suresh, W. Burleson, Robust Metastability-based TRNG Design in Nanometer CMOS with Sub-Vdd Pre-charge and Hybrid Self-calibration, at International Symposium on Quality Electronic Design, ISQED, 2012 pdf

2011

  • G. T. Becker, A. Lakshminarasimhan, L. Lin, S. Srivathsa, V. B. Suresh, W. Burleson, Implementing Hardware Trojans: Experiences from a Hardware Trojan Challenge, 29th IEEE International Conference on Computer Design (ICCD), Amherst, USA, 2011. IEEE

  • J. Jang, W. Burleson, An arbiter based on-chip droop detector system, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2011. acm

  • V. Suresh, W. Burleson, A Hybrid Self-calibration Technique to Mitigate the Effect of Variability in TRNG, 2nd European Workshop on Variability, VARI 2011. pdf

  • B. Datta, W. Burleson, A Tunable Glitch Filtering Circuit Using Variable Threshold Inverters, IEEE International Symposium on Circuits and Systems (ISCAS), Rio De Janeiro, 2011. pdf

  • B. Datta, W. Burleson, A High Sensitivity and Process Tolerant Thermal Sensing Scheme for Liquid Cooled 3-D ICs, ACM Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, 2011. pdf

  • B. Datta, W. Burleson, A 45.6u^2 13.4uW 7.1V/V Resolution Sub-Threshold Based Digital Process Sensor in 45nm CMOS, ACM Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, 2011. pdf

  • B.Datta, W.Burleson, A 12.4um^2 133.4uW 4.56mV/ºC Resolution Digital On-Chip Thermal Sensor in 45nm CMOS Utilizing Sub-Threshold Operation, IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, 2011. pdf

  • G.T. Becker, W. Burleson, C. Paar, Side-channel Watermarks for Embedded Software, 9th IEEE NEWCAS Conference, June 2011. pdf

  • K. Chillara, J. Jang, W. Burleson, Robust Signaling Techniques for Through Silicon Via Bundles, ACM Great Lakes Symposium (GLSVLSI), 2011. pdf

2010

  • V. Suresh, W. Burleson, Entropy Extraction in Metastability-based TRNG, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2010. pdf

  • L. Lin, D.E. Holcomb, D.K. Krishnappa, P. Shabadi, W. Burleson, Low-power sub-threshold design of secure physical unclonable functions, International Symposium on Low Power Electronics and Design (ISLPED), 2010. ACM

  • G.T. Becker, M. Kasper, A. Moradi, and C. Paar, Side-channel based watermarks for integrated circuits, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2010. Also presented at the Workshop on Secure Component and System IdentificationSECSI, 2010. IEEE

  • B. Datta, W. Burleson, Calibration of On-Chip Thermal Sensors using Process Monitoring Circuits, IEEE International Symposium on Quality Electronic Design (ISQED), 2010. IEEE

  • B. Datta, W. Burleson, Circuit-level NBTI Macro-Models for Collaborative Reliability Monitoring, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2010. ACM

  • B. Datta, W. Burleson, Analysis and Mitigation of NBTI Impact on PVT Variability in Global Interconnect Performance, ACM Great Lakes Symposium on VLSI (GLSVLI), 2010. ACM

  • J. Zhao, B. Datta, R. Tessier and W. Burleson, Thermal Aware Voltage Droop Compensation for Multi-Core Architectures, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2010. ACM

2009

  • L. Lin, M. Kasper, T. Güneysu, C. Paar, W. Burleson, Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering, International Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2009. ACM

  • L. Lin, W.P. Burleson, Analysis and mitigation of process variation impacts on Power-Attack Tolerance, Design Automation Conference (DAC), 2009. ACM

  • L. Lin, W. Burleson, C. Paar, MOLES: Malicious off-chip leakage enabled by side-channels, International Conference on Computer-Aided Design (ICCAD), 2009. IEEE

  • B.Datta, W. Burleson, On Temperature Planarization effect of Copper Dummy Fills in Deep Nanometer Technology, IEEE International Symposium on Quality Electronic Design (ISQED), 2009. ACM

  • B. Datta, W. Burleson, Temperature Effects on Energy Optimization in Sub-Threshold Circuit Design, IEEE International Symposium on Quality Electronic Design (ISQED), 2009. ACM

  • B. Datta, W. Burleson, Low-Power, Process-Variation Tolerant On-Chip Thermal Monitoring using Track and Hold Based Thermal Sensors, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2009. ACM

2008

  • B. Datta, W. Burleson, Temperature Measurement in Content Addressable Memory Cells using Bias Controlled VCO, IEEE International System-On-Chip Conference (SOCC), 2008. IEEE

  • J. Jang, O. Franza (Intel), W. Burleson, Period Jitter in Global Clock Trees, IEEE Workshop on Signal Propagation on Interconnects (SPI), 2008. IEEE

  • L. Lin, and W. Burleson, Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems, IEEE International Symposium on Circuits and Systems, 2008. IEEE

  • V. Arunachalam and W. Burleson, Low-Power Clock Distribution in a Multilayer Core 3D Microprocessor, ACM Great Lakes Symposium on VLSI, 2008. ACM

  • B. Datta and W. Burleson, Collaborative Sensing of On-Chip Wire Temperatures using Interconnect based Ring Oscillators, ACM Great Lakes Symposium on Circuits and Systems, 2008. ACM

2007

  • V. Ambrose, W. Burleson, D. Holcomb, S. Mukherjee, J. Pickholtz, A Fast and Accurate Method for Simulating Soft Errors in Large Combinational Circuits, Intel Design and Test Technology Conf., 2007.

  • D.E. Holcomb, W. Burleson, K. Fu, Initial SRAM state as a fingerprint and source of true random numbers for RFID tags, Proceedings of the Conference on RFID Security, 2007. pdf

  • S. Xu, I. Benito, W. Burleson, Thermal Impacts on NoC Interconnects, Poster at the First International Symposium on Networks-on-Chip, 2007. IEEE

  • D. Kumar and W. Burleson, Distributed Collaborative Adaptive Sensing: A Unifying Theme for a Junior Level Embedded Systems Course, IEEE Microelectronics Systems Education Conference, 2007. IEEE

  • B. Datta, W. Burleson, Low Power and Robust On-Chip Thermal Sensing using Differential Ring Oscillators, International Mid-West Symposium on Circuits and Systems, 2007. IEEE

  • B. Datta, W. Burleson, Low Power On-Chip Thermal Sensors based on Wires, International Conference on VLSI-SoC, October 2007. IEEE

  • B.Datta, W.Burleson, ThermoWire: A Fast, Robust, low-power Interconnect based thermal sensor, IEEE VLSI-SoC October, 2007.

  • V. Venkatraman and W. Burleson, An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects, IEEE Custom Integrated Circuits Conference (CICC), Sept 2007. IEEE

  • R. Vaslin, G. Gogniat, J.-P. Diguet, W. Burleson, and R. Tessier, High-Efficiency Protection Solution for Off-Chip Memory in Embedded Systems, in the Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, June 2007. pdf

  • R. Vaslin, G. Gogniat, J.-P. Diguet, E. Wanderley, R. Tessier and W. Burleson, Low Latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory, in the Proceedings of the International Conference on Reconfigurable Communication-centric SoCs, Montpellier, France, June 2007. pdf

2006

  • I. Benito, V. Venkatraman, W. Burleson, Process Variation-Aware Vdd Assignment Technique for Repeated Interconnects, 49th IEEE International Midwest Symposium on Circuits and Systems, 2006. IEEE

  • S. Xu, V. Venkatraman and W. Burleson, Energy-Aware Differential Current Sensing for Global On-Chip Interconnects, 49th IEEE International Midwest Symposium on Circuits and Systems, 2006. IEEE

  • Tilman Wolf, Shufu Mao, Dhruv Kumar, Basab Datta, Wayne Burleson, and Guy Gogniat. Collaborative monitors for embedded system security, In Proc. of First International Workshop on Embedded Systems Security in conjunction with 6th Annual ACM International Conference on Embedded Software (EMSOFT), Seoul, Korea, October 2006. pdf

  • V. Venkatraman, M. Anders, H. Kaul, W. Burleson, R. Krishnamurthy, A low-swing signaling circuit technique for 65nm on-chip interconnects, IEEE International SOC Conference, Sept. 2006: 289-292. IEEE

  • G. Gogniat, T. Wolf, and W. Burleson, Reconfigurable Security Architecture for Embedded Systems, Mobile Computing Hardware Architectures: Design and Implementation Design Symposium (MOCHA 2006), January, 2006. pdf

2005

  • G. Gogniat, T. Wolf, and W. Burleson, Reconfigurable Security Primitive for Embedded Systems, IEEE International Symposium on System-on-Chip (SOC 2005) November, 2005. IEEE

  • Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark Anders, Saurabh Dighe, Wayne Burleson, Ram Krishnamurthy, A 2GHz 13.6mW 12x9b Multiplier for Energy Efficient FFT Accelerators, Proc. of the 31st European Solid-State Circuits Conference, Sep. 2005. IEEE

  • Vishak Venkatraman and Wayne Burleson, Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations, Sixth International Symposium on Quality of Electronic Design, March 2005, pp: 522-527 IEEE

  • Jinwook Jang, Sheng Xu, Wayne Burleson, Jitter in Deep Sub-micron Interconnect, IEEE Computer Society Annual Symposium on VLSI, 2005. IEEE

  • Wayne Burleson and Sheng Xu, Digital Systems Design with ASIC and FPGA: A Novel Course using CD/DVD and On-line Formats, International Conference on Microelectronic Systems Education, 2005. IEEE

  • Vishak Venkatraman and Wayne Burleson, Impact of Process Variations on Multi-level Signaling for On-Chip Interconnects, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005. IEEE

  • Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson, Sensing Design Issues in Deep Submicron CMOS SRAMs, IEEE Computer Society Annual Symposium on VLSI, 2005. IEEE

  • N. Salzmann, W. Burleson, K. Rubin, K. Kloesel, S. Cruz-Pol, O. El-Hakim, Challenges in a Multidisciplinary K12 Summer Content Institute, ASEE 2005.

  • B. Wallace, W. Richards Adrion, W. Burleson, W. Cooper, J. Cori and K. Watts, Using Multimedia to Support Research, Education and Outreach in an NSF Engineering Research Center, Frontiers in Education (FIE), 2005. IEEE

  • G. Gogniat, L. Bossuet, and W. Burleson, Configurable computing for high-security/high-performance ambient systems, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS V) July, 2005. pdf

  • W. Burleson, T. Wolf, R. Tessier, W. Gong, G. Gogniat, Embedded System Security: A Configurable Approach, International Conference on Homeland Security, 2005. pdf

  • O. Hoffman, T. Djaferis, P. Dobosh, W. Burleson, Moving towards a more Systems Approach in a Robotics based Introductory Engineering Course at Mt. Holyoke College, ASEE 2005.

  • N. Salzmann, W. Burleson, K. Rubin, K. Kloesel, S. Cruz-Pol, O. El-Hakim, Challenges in a Multidisciplinary K12 Summer Content Insitute, ASEE 2005.

2004

  • Vishak Venkatraman, Atul Maheshwari , Wayne Burleson, Mitigating Static-Power in Current-Sensed Interconnects, ACM Great Lakes Symposium on VLSI 2004. ACM

  • Matthew W. Heath, Wayne P. Burleson and Ian G. Harris, Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC’s, Proceedings of Design, Automation and Test in Europe (DATE), Vol. 1, Feb. 2004, pp. 410 - 415. IEEE

  • Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Zhi Zhu, Hempraveen Kukkamalla, Wayne Burleson, NoCIC: A Spice-based Interconnect Planning Tool Emphasizing Aggressive On-Chip Interconnect Circuit Methods, 6th International workshop on System Level Interconnect Prediction, 2004. ACM

  • M. Heath, W. Burleson and I. Harris, A Deterministic Globally Asynchronous Locally Synchronous (GALS) Methodology for Validation, Debug, and Test, Design Automation and Test in Europe, 2004

  • L. Bossuet, G. Gogniat, W. Burleson, Dynamically Configurable Security for SRAM FPGA Bitstreams, Reconfigurable Architectures Workshop, 2004. IEEE

  • A. Maheshwari, I. Koren, W. Burleson, Accurate Estimation of Soft Error Rates (SER) in VLSI Circuits, IEEE Conference on Defect and Fault-tolerance in VLSI, 2004. IEEE

2003

  • Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne Burleson, Ram Krishnamurthy, Shekhar Borkar, High-Performance and Low Voltage Sense-Amplifier Techniques for Sub-90nm SRAM, IEEE ASIC SOC Conference, 2003. IEEE

  • Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne Burleson Ram Krishnamurthy, Shekhar Borkar, Low Voltage Sensing Techniques and Secondary Design Issues for Sub-90nm Caches, European Solid State Circuits Conference, 2003. IEEE

  • Atul Maheshwari and Wayne Burleson, Repeater and Current-sensing Hybrid Circuits for On-chip Interconnects, ACM Great Lakes Symposium on VLSI, 2003. ACM

  • Aiyappan Natarajan, David Jasinski, Wayne Burleson and Russell Tessier, A Hybrid Adiabatic Content Addressable Memory for Ultra Low-power Applications, ACM Great Lakes Symposium Symposium on VLSI, 2003. ACM

  • Srividya Srinivasaraghavan and Wayne Burleson, Interconnect Effort - A Unification of Repeater Insertion and Logical Effort, IEEE International Symposium on VLSI, 2003. IEEE

  • J. Chittamuru, and W. Burleson, Dynamic Wordlength Variation for Low-Power 3D Graphics Texture Mapping, IEEE Workshop on Signal Processing Systems, 2003. IEEE

  • A. Laffely and W. Burleson, Using System-on-a-Chip as a Vehicle for VLSI Education, IEEE Microelectronic Systems Education Conference, June 2003. IEEE

  • A. Laffely, J. Liang, W. Burleson, R. Tessier, Adaptive System on a Chip: A Backbone for Power-Aware Signal Processing Cores, IEEE International Conference on Image Processing, September 2003. IEEE

  • A. Natarajan, D. Jasinski, W. Burleson, R. Tessier, A Hybrid Adiabatic Content Addressable Memory for Ultra-Low Power Applications, ACM Great Lakes Symposium on VLSI, 2003. ACM

  • A. Maheshwari and W. Burleson, Repeater and Current-sensing Hybrid Circuits for On-chip Interconnects, ACM Great Lakes Symposium on VLSI, 2003. ACM

2002

  • Atul Maheshwari, Srividya Srinivasaraghavan and Wayne Burleson, Quantifying the Impact of Current-Sensing on Interconnect Delays Trends, IEEE ASIC SOC Conference, 2002. IEEE

  • A. Maheshwari, W. Burleson, R. Tessier, Trading Off Power and Reliability in Ultra-Low Power Systems, IEEE International Symposium on Quality in Electronic Design, March 2002. IEEE

  • S. Swaminathan, R. Tessier, D. Goeckel, W. Burleson, An Adaptive Viterbi Decoder in FPGAs, FPGA Conference, 2002.

  • J. Chittamuru, J. Euh, and W. Burleson, An Adaptive Low Power Texture Mapping Architecture, IEEE Mid-West Symposium On Circuits and Systems, 2002 pp. 204-208 IEEE

  • J. Euh, J. Chittamuru, and W. Burleson, CORDIC Vector Interpolator for Power-Aware 3D Computer Graphics, IEEE Workshop on Signal Processing Systems, 2002 pp. 426-431. IEEE

  • W. Burleson, S. Kelley, S. Thampuran, A New Course in Multimedia Systems for Non-Technical Majors, ASEE Engineering Education Conference and Exposition, June 2002, pp. 2793-2802.

  • W. Burleson, W. Cooper, J. Kurose, S. Thampuran, K. Watts, An Empirical Study of Student Interaction with CD-based Multimedia Courseware, ASEE Engineering Education Conference and Exposition, June 2002. pp 1430-1443

  • W. Burleson, S. Thampuran N. Ramaswamy, Multimedia Systems: Enabling Computer Engineering Education, IEEE Frontiers in Education Conference, 2002. IEEE

2001

  • W. Burleson, P. Jain, S. Venkatraman, Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT, IEEE Workshop on Digital and Computational Video, 2001. IEEE

  • W. Burleson, R. Tessier, D. Goeckel, P. Jain, A. Laffely, Dynamically Parameterized Algorithms and Architectures for Low-Power Signal Processing, International Conference on Acoustics Speech and Signal Processing, 2001

  • Manoj Sinha and Wayne Burleson, Current-Sensing for Crossbars, IEEE ASIC SOC Conference, 2001. IEEE

  • Ankireddy Namalpu and Wayne Burleson, A Practical Approach to DSM Repeater Insertion: Satisfying Delay Constraints while Minimizing Area and Power, IEEE ASIC SOC Conference, 2001 IEEE

  • Ankireddy Namalpu and Wayne Burleson, BOOSTERS: An Alternative to Repeaters for Driving Long On-Chip Interconnects, IEEE International Symposium on Physical Design, 2001.

  • Atul Maheshwari and Wayne Burleson, Current-sensing for Global Interconnects, Secondary Design Issues: Analysis and Solutions, IEEE International Workshop on power and timing modeling, optimization and simulation, 2001.

  • Atul Maheshwari and Wayne Burleson, Current Sensing Techniques for Global Interconnects in Very Deep Submicron (VDSM) CMOS, IEEE Computer Society Workshop on VLSI, 2001. IEEE

  • Ankireddy Nalamalpu and Wayne Burleson, Repeater Insertion in deep sub-micron CMOS: Ramp-based Analytical Model and Placement Sensitivity Analysis, IEEE International Symposium on Circuits and Systems, 2000. IEEE

  • S. Thampuran, K. Watts, W. Burleson, CD-MANIC: Multimedia Distance Learning without the Wait, IEEE Frontiers in Education, 2001. IEEE

  • A. Laffely, W. Burleson, R. Tessier, J. Liang, Adaptive System on a Chip for Low-Power Signal Processing, Asilomar Conference on Signal and Systems, October 2001

2000

  • J. Euh, W. Burleson, Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. Workshop on Power-Aware Computing, Fall 2000.

  • J. Peden, W. Burleson, C. Leonardo, The Multimedia Online Collaboration Architecture: Tools to Enable Distance Learning, International Conference on Multimedia and Exposition, Aug, 2000.

  • A. Nalamalpu and W. Burleson, Repeater Design in DSM CMOS: Novel Analytical Model and Placement Sensitivity Analysis, International Symposium on Circuits and Systems, 2000.

  • W. Burleson, J. Peden, C. Leonardo, Distributed VLSI Design with the Multimedia Online Collaboration Architecture, European Workshop on Microelectronics Education, May 2000.

  • R. Adrion, J. Kurose, W. Burleson, et al , Multimedia Asynchronous Networked Information Courseware, UMass Instructional Technology Conference, 2000.

  • J. Peden, C. Leonardo, W. Burleson, The Multimedia Online Collaboration Architecture, UMass Instructional Technology Conference, 2000.

  • A. Garcia, W. Burleson, J. Danger, Low Power Digital Design in FPGAs: A Study of Pipeline Architectures Implemented in a FPGA Using a Low Supply Voltage to Reduce Power Consumption, FPGA Conference, 2000. Updated version presented at ISCAS, 2000.

1999

  • W. Burleson, A. Ganz, I. Harris, Educational Innovations in Multimedia Systems, Frontiers in Education Conference, 1999. (Winner of Ben Dasher Award for Best Paper at entire conference.)

  • A. Garcia, W. Burleson, J.L. Danger, Power Modelling in FPGAs, International Conference on Field Programmable Logic and Applications, 1999.

  • W. Burleson, A. Ganz, I. Harris, Multimedia Systems: An Integrated Modular Curriculum, University of Massachusetts Instructional Technology Conference 1999.

  • S. R. Park and W. Burleson, Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures, FPGA Conference, 1999.

1998

  • A. Garcia, W. Burleson, J.L. Danger, Modele de la consommation de puissancedes FPGA, Journees D'Etude Faible Tension, Faible Consommation, Paris, France. 1998, (in French).

  • A. Garcia, W. Burleson, J.L. Danger, Etude sur la consommation de puissance d'un dicodeur MPEG2 ` base des FPGA, Journees D'Etude Faible Tension, Faible Consommation, Paris, France. 1998, (in French).

  • S. R. Park, W. Burleson, Frame-Rate Hardware Reconfiguration for Power Saving in Real-time Motion Estimation, International Conference on Acoustics, Speech and Signal Processing, 1998.

1997

  • A. Brahmbhatt, W. Burleson, FPGA-based Co-processors for Wireless Data Communications, Massachusetts Telecommunications Conference, 1997.

  • M. Petronino, W. Burleson, J. Carswell, J. Mead, R. Bambha, FPGA-based Data Acquisition for 95Ghz Polarimetic Radar, International Conference on Acoustics, Speech and Signal Processing, 1997.

  • W. Burleson and M. Ciesielski, Using Computers to Design Computers: Novel Instructional Technology in Computer Systems Engineering, UMASS Instructional Technology Conference, 1997.

1996

  • B. Jung and W. Burleson, VLSI Array Architectures for Pyramid Vector Quantization, VLSI Signal Processing Workshop 1996.

  • W. Burleson, Integrating Manufacturing into a Computer Systems Design Course: Design Technology and Industrial Collaboration, IEEE Frontiers in Education Conference, 1996.

  • M. Stan, and W. Burleson, Two-dimensional Codes for Low-Power, International Symposium on on Low-Power Electronics and Design, 1996.

  • M. Stan, Wayne P. Burleson, Synchronous Up/Down Counter with Period Independent of Counter Size, FPGA Conference, 1996.

1995

  • M. Stan, and W. Burleson, Low-Power CMOS Clock Drivers, ACM Workshop on Timing in Digital Systems, 1995.

  • T. Kim, W. Burleson and M. Ciesielski, Constrained Timing Synthesis and Delay insertion with Application to Wave-pipelining, ACM Workshop on Timing in Digital Systems, 1995.

  • R. Grupen, C. Connolly, K. Souccar, and W. Burleson, Toward a Path Co-Processor for Automated Vehicle Control, IEEE Symposium on Intelligent Vehicles, 1995.

  • Z. Zhou , W. Burleson, Equivalence Checking of Datapaths based on Canonical Arithmetic Expressions, Design Automation Conference, San Francisco, 1995.

  • M. Stan and W. Burleson, Coding a terminated bus for Low-power, Great Lakes Symposium on VLSI, 1995.

  • Y. Jeong, W. Burleson, High-level Estimation of High-Performance Architectures for Reed-Solomon Decoding, International Symposium on Circuits and Systems, 1995. pp. I-720-723.

  • B. Jung, W. Burleson, Real-Time VLSI Compression for Wireless Local Area Networks, Data Compression Conference, 1995. p 431.

1994

  • W. Burleson, M. Ciesielski, W. Cotten and F. Klass, Is Wavepipelining Practical?, (A forum session), Proceedings of International Symposium on Circuits and Systems, 1994.

  • H. Choi and W. Burleson, Search-based Wordlength Optimization in VLSI/DSP Synthesis, VLSI Signal Processing Workshop, 1994.

  • W. Burleson, C. Lee and E. Tan, A 150 Mhz Wave-pipelined Adaptive Digital Filter in 2 micron CMOS, VLSI Signal Processing Workshop, 1994.

  • B. Jung, Y. Jeong and W. Burleson, Distributed Control Synthesis for Data-Dependent Iterative Algorithms, Conference on Application-Specific Array Processors, 1994.

  • M. Stan and W. Burleson, Limited-weight codes for low-power I/O, International Workshop on Low-Power Design, 1994.

  • B. Jung and W. Burleson, A VLSI Systolic Array Architecture for Lempel-Ziv-based Data Compression, International Symposium on Circuits and Systems, 1994.

  • W. Burleson, Using Regular Array Methods for DSP Module Synthesis, Hawaii International Conference on System Sciences, 1994, p. I-58-67 (an invited session).

1993

  • T. S. Kim, W. Burleson, and M. Ciesielski, Delay buffer insertion for Wave-pipelined Circuits, International IFIP Workshop on Logic and Architecture Synthesis, France 1993.

  • D. Niehaus, K. Ramamritham, J. Stankovic, G. Wallace, C. Weems, W. Burleson, J. Ko, The Spring Scheduling Coprocessor: Design, Use and Performance, Proceedings of the Real Time Systems Symposium, 1993.

  • W. Marvin, W. Burleson, D.S. Phatak, Full Simulation of Optical Neural Nets, Proc. of SPIE Conference on Neural Networks, 1993.

  • H. Choi, W. Burleson, D.S. Phatak, Fixed-Point Roundoff Error Analysis of Large Feedforward Neural Nets, International Joint Conference on Neural Networks, 1993.

  • Z. Zhou, W. Burleson, Formal Descriptions, Semantics and Verification of VLSI Array Processors, International Conference on Application-Specific Array Processors, 1993, pp. 321-332.

  • B. Jung, W. Burleson, Node-Merging: A Transformation on Bit-level Dependency Graphs, International Conference on Application-Specific Array Processors, 1993, p. 442-453.

  • Y. Jeong, W. Burleson, VLSI Array Synthesis for Polynomial GCD Computation, International Conference on Application-Specific Array Processors, 1993, p. 536-547, (1 of 19 full-length papers accepted out of 121 submitted).

  • H. Choi, W. Burleson, D.S. Phatak, Optimal Wordlength Assignment for the Discrete Wavelet Transform in VLSI, Workshop on VLSI Signal Processing, 1993, p. 325-333.

  • W. Burleson, J. Ko, D. Niehaus, K. Ramamritham, J. Stankovic, G. Wallace, C. Weems, The Spring Scheduling Coprocessor: A Scheduling Accelerator, International Conference on Computer Design, 1993, p. 140-144.

  • T. S. Kim, W. Burleson, M. Ciesielski, Logic Restructuring for Wave-pipelining, International Workshop on Logic Synthesis, 1993.

  • J. D. Narkiewicz, W. Burleson, Rank-Order Filtering Algorithms: A Comparison of VLSI Implementations, International Symposium on Circuits and Systems, 1993.

  • J. D. Narkiewicz, W. Burleson, VLSI Performance/Precision Tradeoffs of Approximate Rank-Order Filters, Workshop on VLSI Signal Processing, p. 185-194.

1992

  • M. Stan, W. Burleson, Analog VLSI for Robot Path Planning, Asilomar Conference on Signals, Systems and Computers, 1992, p. 915-919.

  • W. Burleson, B. Jung, ARREST: An Interactive Graphic Design Tool for VLSI Arrays, International Conference on Application Specific Array Processors, 1992, p. 149-162.

  • Y.Jeong, W. Burleson, Choosing VLSI Algorithms for Finite Field Arithmetic, International Symposium on Circuit and Systems, 1992, p. 799-802.

  • W.-H. Lien, W. Burleson, Wave-Domino Logic: Theory and Application, International Symposium on Circuit and Systems, 1992, p. 2949-2952. (also presented at ACM/SIGDA Workshop on Timing Issues in the Specification of Digital Systems, 1992)