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Embedded System Security Group



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Security for SRAM FPGA Bitstreams

FPGAs are becoming increasingly attractive thanks to the improvement of their capacities and performances.
Today they represent an efficient design solution for numerous systems. However, it becomes necessary to improve their security particularly for SRAM FPGAs, since they are more vulnerable than other FPGA technologies. This work proposes a solution to improve the security of SRAM FPGAs through a flexible bitstream encryption. This proposition is distinct from other works because it uses the latest capabilities of SRAM FPGAs like partial dynamic reconfiguration and self-reconfiguration. It does not need an external battery to store the secret key. It opens a new way of application partitioning oriented by the security policy.

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Configurable computing for security

This work stresses why configurable computing is a promising target to guarantee the hardware security of ambient systems. Many works have focused on configurable computing to demonstrate its efficiency but as far as we know none have addressed the security issue from system to circuit levels. Two complementary views are proposed to provide a guide for security and main issues to make them a reality are discussed. The goal of this work is to make designers aware of that configurable computing is not just hardware accelerators for security primitives as most studies have focused on but a real solution to provide high-security/high-performance for the whole system.


This work was supported by the French DGA  DSP/SREA under contract no. ERE 04 60 00 010


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Reconfigurable Security Architecture for Embedded Systems

Embedded systems present significant security challenges due to their limited resources and power constraints. We propose a novel security architecture for embedded systems (SANES) that leverages the capabilities of reconfigurable hardware to provide efficient and flexible architectural support to both security standards and a range of attacks. This work shows the efficiency of reconfigurable architecture to implement security primitives within embedded systems. We also propose the use of hardware monitors to detect and defend against attacks. The SANES architecture is based on three main ideas: 1) reconfigurable security primitives, 2) reconfigurable hardware monitors and 3) a hierarchy of security controllers at the primitive, system and executive level.


This work was supported by the French DGA  DSP/SREA under contract no. ERE 04 60 00 010


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NoC Security

This work addresses the new kind of security vulnerable spots introduced by Network-on-chip (NoC) use in System-on-Chip (SoC) design. This work is based on the experience of a CAD framework for NoC design and proposes a classification of weaknesses with regard to usual routing and interface techniques. Finally design strategies are proposed and a new path routing technique (SCP) is introduced with the aim to enforce security.


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