Vlsi Circuits And Systems Group

Journal Papers

2015 2013 2012 2011 2010 2009 2008 2007 2005 2004 2002 2000 1998 1997 1995 1994


  • X. Xu, A. Rahmati, D. Holcomb, K. Fu, W. Burleson. Reliable Physical Unclonable Functions using Data Retention Voltage of SRAM Cells. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), 2015, to appear.


  • U. Ruhrmair, J. Solter, F. Sehnke, X. Xu, A. Mahmoud, V. Stoyanova, G. Dror, J. Schmidhuber, W. Burleson, and S. Devadas. PUF modeling attacks on simulated and silicon data. IEEE Transactions on Information Forensics & Security (T-IFS), November 2013. PDF


  • M. Kasper, A. Moradi, G. T. Becker, O. Mischke, T. Güneysu, C. Paar and W. Burleson, Side Channels as Building Blocks, Journal of Cryptographic Engineering, Volume 2, Number 3, pages 143-159, 2012, Springer PDF

  • G. T. Becker, D. Strobel, C. Paar and W. Burleson Detecting Software Theft in Embedded Systems: A Side-Channel Approach, IEEE Transactions on Information Forensics & Security (T-IFS), August 2012. PDF

  • L. Lin, S. Srivathsa, D. K. Krishnappa, P. Shabadi, w. Burleson Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications , IEEE Transactions on Information Forensics & Security (T-IFS), August 2012. PDF


  • B. Datta and W. Burleson, Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies , Journal of Low Power Electronics 7, 403-419, 2011. ingentaconnect

  • J. Zhao, S. Madduri, R. Vadlamani, W. Burleson, R. Tessier, A Dedicated Monitoring Infrastructure For Multicore Processors, IEEE Transactions on VLSI Systems, 2011. IEEE


  • J. Jang, O. Franza, W. Burleson, Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees, IEEE Transactions on VLSI Systems, 2010. IEEE


  • D. Holcomb, K. Fu, W. Burleson Power-up SRAM State as an Identifying Fingerprint and Source of True Random Numbers, IEEE Transactions on Computers. IEEE


  • G. Gogniat, T. Wolf, W. Burleson, J. Diguet, L. Bossuet and R. Vaslin, Reconfigurable hardware for high-security/high-performance embedded systems: The SAFES perspective, IEEE Transactions on VLSI, Vol. 16, Number 2, February 2008. IEEE


  • A. Maheshwari and W. Burleson, Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects, IEEE Transactions on VLSI, November, 2007.


  • D. Jasinski, A. Maheshwari, A. Natarajan, W. Xu, R. Tessier, W. Burleson, An Energy-Aware Active Smart Card, IEEE Transactions on VLSI, October 2005. IEEE

  • M. W. Heath, W. P. Burleson and I. G. Harris, Synchro-tokens: a deterministic GALS methodology for chip-level debug and test, IEEE Transactions on Computers, Vol. 54, Issue 12, Dec 2005, pp. 1532 - 1546. IEEE

  • S. Swaminathan, R. Tessier, D. Goeckel, W. Burleson, A Reconfigurable Viterbi Decoder in FPGAs, IEEE Transactions on VLSI Systems. Volume 13, Issue 4, pp.484 – 488, April 2005.

  • L. Bossuet, G. Gogniat, W. Burleson, Dynamically Configurable Security for SRAM FPGA Bitstreams, International Journal of Embedded Systems. Issue 5/6 of 2005. IEEE

  • J. Chittamuru, J. Euh and W. Burleson, Power-Aware 3D Graphics Rendering, Journal of VLSI Signal Processing Systems, January, 2005.


  • A. Maheshwari and W. Burleson, Differential current-sensing for on-chip interconnects, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12,  Issue 12,  Dec 2004, pp. 1321 - 1329.  IEEE

  • A. Maheshwari, W. Burleson and R. Tessier, Trading-off Transient Fault-tolerance and Power Consumption in Deep Submicron (DSM) VLSI Circuits, IEEE Transactions on VLSI Systems, volume 12, Issue 3, pp.299-311, March 2004. IEEE

  • P. Jain,A. Laffely,W. Burleson,R. Tessier,and D. Goeckel, Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations, Journal of VLSI Signal Processing Systems, vol 36, no. 1, pages 27-40, January 2004.


  • Ankireddy Nalamalpu, Sriram Srinivasan and Wayne Burleson, Boosters for Driving Long On-chip Interconnects: Design Issues, Interconnect Synthesis and Comparison with Repeaters, IEEE Transactions on Computer Aided Design, Vol. 21, Issue 1, Jan 2002, pp. 50 - 62. IEEE


  • Ankireddy Nalamalpu and Wayne Burleson, Quantifying and Mitigating the effects of Repeater Placement constraints on interconnect Performance, IEEE Transactions on VLSI Systems, 2000. 

  • R. Tessier and W. Burleson, Reconfigurable Computing for Digital Signal Processing: A Survey, Journal of VLSI Signal Processing Systems, Fall 2000.

  • W. Burleson, A. Ganz and I. Harris, Educational Innovations in Multimedia Systems, Journal of Engineering Education, Winter 2000.


  • W. Burleson, J. Ko, D. Niehaus, K. Ramamritham, J. Stankovic, G. Wallace, C. Weems The Spring Scheduling Co-Processor: A Scheduling Accelerator, IEEE Transactions on VLSI, November, 1998.

  • B. Jung, W. Burleson, VLSI Architectures for Pyramid Vector Quantization, Journal of VLSI Signal Processing Systems, Winter 1998.

  • B. Jung, W. Burleson, Performance Optimization of Wireless Local Area Networks through VLSI Data Compression, ACM Wireless Networks Special Issue on VLSI in Wireless Networks, Winter 1998. ACM

  • W. Burleson, M. Ciesielski, F. Klass, W. Liu, Wave-pipelining in VLSI: A Survey and Tutorial, IEEE Transactions on VLSI Systems, Sept, 1998. IEEE

  • B. Jung, W. Burleson, VLSI Algorithm, Architecture and Implementation for High-Speed Lempel-Ziv Data Compression, IEEE Transactions on VLSI Systems, Sept 1998.


  • M. Stan, W. Burleson Low-Power Encodings for Global Communication in CMOS VLSI, IEEE Transactions on VLSI Systems, vol 5, no 4, Dec. 1997, pp. 444-455.

  • Y. Jeong and W. Burleson, Array Algorithms and Architectures for RSA Modular Multiplication based on Precalculated Complements of the Modulus, IEEE Transactions on VLSI Systems, June 1997.


  • M. Stan, W. Burleson, Bus-Invert Method for Low-Power I/O, IEEE Transactions on VLSI Systems, March, 1995, Vo. 3, No 1, pp 49-58.

  • W.-H. Lien, W. Burleson,Wave-Domino Logic: Theory and Application, IEEE Transactions on Circuit and Systems II, February, 1995, Vo. 42, No 2, pp 78-91.


  • Y. Jeong, W. Burleson,VLSI Array Synthesis for Polynomial GCD computation and Application to Finite Field Division, IEEE Transaction on Circuits and Systems II, December 1994, Vol 41.

  • M. Stan, W. Burleson, C. Connolly, R. Grupen, Analog VLSI for Robot Path Planning, Journal of VLSI Signal Processing, 8, 61-73 (1994).