Adaptive System on a Chip
As on-chip integration
matures, single-chip system designers must not only be concerned with component-level issues such as performance and power but also with on-chip system-level issues such as adaptability and scalability. Recent trends indicate that next generation systems will require new architectures and compilation tools that effectively deal with these constraints. This site provides links to our new single-chip interconnect architecture, adaptive System-On-a-Chip.
This architecture has been shown to be up to 5 times more efficient than bus-based SoC interconnect architectures.
This material is based upon work supported by the National Science Foundation under Grant No. 9988238. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
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