Publications by Project:

Thesis

Andrew Laffely, “An Interconnect-centric Approach for Adapting Voltage and Frequency in Heterogeneous System-on-a-Chip”, (pdf), (ps), Ph.D. thesis, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, August 2003.

Jian Liang, “Development and Verification of System-On-a-Chip Communication Architecture”, Ph.D. thesis, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, February 2004.

Architecture

Andrew Laffely, Jian Liang, Russell Tessier and Wayne Burleson "Adaptive System on a Chip (aSoC): a Backbone for Power-Aware Signal Processing Cores", (pdf), Slides, The IEEE International Conference on Image Processing, Barcelona, Spain, Sep. 2003

Andrew Laffely, Wayne Burleson, "Using System-on-a-Chip as a Vehicle for VLSI Design Education", (pdf), Slides, International Conference on Microelectronic Systems Education Workshop, Anaheim, California, June 2003

Andrew Laffely, Jian Liang, Russell Tesser, Csaba Andras Moritz, Wayne Burleson, "Power-Aware System on a Chip", (ppt) Presented at Boston Area Architecture Workshop Jan. 2003

Andrew Laffely, Jian Liang, Prashant Jain, Ning Weng, Wayne Burleson, Russell Tessier, "Adaptive System on a Chip (aSoC) for Low-Power Signal Processing", (pdf), Slides.ppt, Thirty-Fifth Asilomar Conference on Signals, Systems, and Computers, Nov. 4-7, 2001

Jian Liang, Sriram Swaminathan, and Russell Tessier, "aSoC: A Scalable, Single-Chip Communications Architecture", (ps), Proceedings, International Conference on Parallel Architectures and Compilation Techniques, Philidelphia, PA, Oct., 2000

Application Mapping

L. Bossuet, W. Burleson, G. Gogniat, V. Anand, A. Laffely and J.L. Philippe, "Targeting Tiled Architectures in Design Exploration", Sent for consideration to Proceedings, Reconfigurable Architectures Workshop, Nice, France, Apr. 2003

Interconnect

Manoj Sinha and Wayne Burleson, "Current-Sensing for Crossbars", ASIC System on a Chip ps-file (333 kB) , pdf-file (163kB).

Application

Jeongseon Euh, Jeevan Chittamuru and Wayne Burleson, "Power-Aware 3D Computer Graphics Rendering", (Draft PDF(342KB), PS(9.8 MB), Invited to JVSP Special-Issue on SIPS 2002), Feb 2003.

Prashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier, Dennis Goeckel, "Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations" Sent for consideration in JVSP Feb 2002

Prashant Jain, "Parameterized Motion Estimation Architecture for Dynamically Varying Power and Compression Requirements" Masters Thesis, University of Massachusetts Dec. 2001

Subramanian Venkatraman, "A Power-Aware Synthesizable Core for the Discrete Cosine Transform", Masters Thesis, University of Massachusetts Aug. 2001

Wayne Burleson, Russell Tessier, Dennis Goeckel, Sriram Swaminathan, Prashant Jain, Jeongseon Euh, Subramanian Venkatraman and Vidhya Thyagarajan, "Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations for Improved Performance and Reduced Power"(PDF).

Andrew Laffely, "Dynamic MPEG Encoding Algorithms and Architectures which Leverage Content Variation for Power Savings", (html version) ICASSP '01 Student Forum(PDF)

Wayne P. Burleson, Prashant Jain, Subramanian Venkatraman, "Dynamically Parameterized Architecture for Power-Aware Video Coding: Motion Estimation and DCT"(ps file 1.8Mb), (zip file 300Kb),(pdf 328Kb),(Slides 1.7Mb), Second USF International Workshop on Digital and Computational Video (DCV'01), 2001.

Jeongseon Euh and Wayne Burleson, "Exploiting Content Variation and Perception in Power-aware 3D Graphics Rendering" (pdf file), (gziped PS), (Presentation Slide, best on IE), 2000 Workshop on Power-Aware Computer Systems (PACS'00).

Russell Tessier and Wayne Burleson, "Reconfigurable Computing for Digital Signal Processing: A Survey" (ps file), Special Issue of the Kluwer Journal of VLSI Signal Processing, Fall, 2000.

Sung Ryong Park and Wayne Burleson, "Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures" (ps file), (slide) 1999 International Symposium on Field Programmable Gate Arrays (FPGA '99).

Sung Ryong Park and Wayne Burleson, "Reconfiguration for Power Saving in Real-Time Motion Estimation", ICASSP, May, 1998.

Michael Petronino, Ray Bambha, James Carswell, Wayne Burleson, "An FPGA-based Data Acquisition System for a 95 Ghz W-b and Radar", 1997 Intl. Conference on Acoustics, Speech and Signal Processing (ICASSP), Munich.

Bongjin Jung and Wayne Burleson, "VLSI Array Architectures for Pyramid Vector Quantization", 1996 VLSI Signal Processing Workshop.

Bongjin Jung and Wayne Burleson, "Real-Time VLSI Compression for High-Speed Wireless Local Area Networks", 1995 Data Compression Conference.

Yongjin Jeong and Wayne Burleson, "High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding", ISCAS 95.

Zheng Zhou and W. Burleson, "Equivalence Checking of Datapaths based on Canonical Arithmetic Expressions", Design Automation Conference 95.