Some Recent Research Papers:
- Wayne Burleson, Russell Tessier, Dennis Goeckel, Sriram Swaminathan, Prashant Jain, Jeongseon Euh, Subramanian Venkatraman and Vidhya Thyagarajan "``Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations for Improved Performance and Reduced Power''(PDF), (gziped PS), (without references, PDF), (without references, gziped PS), submitted to International Conference on Acoustics, Speech, and Signal Processing, 2001 (ICASSP'01).
- Wayne P. Burleson,
Prashant Jain, Subramanian Venkatraman "
Dynamically Parameterized Architecture for Power-Aware Video Coding:
Motion Estimation and DCT,"(ps file 1.8Mb), (zip file 300Kb),
(pdf 328Kb),(Slides 1.7Mb),
Second USF International Workshop on Digital and Computational Video
- Jeongseon Euh and Wayne Burleson, ``Exploiting Content Variation and Perception in Power-aware 3D Graphics Rendering'' (pdf file), (gziped PS), (Presentation Slide, best on IE), 2000 Workshop on Power-Aware Computer Systems (PACS'00).
- Russell Tessier and Wayne Burleson, ``Reconfigurable Computing for Digital Signal Processing: A Survey'' (ps file), Special Issue of the Kluwer Journal of VLSI Signal Processing, Fall, 2000.
- Sung Ryong Park and Wayne Burleson, ``Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures'' (ps file), (slide) 1999 International Symposium on Field Programmable Gate Arrays (FPGA '99).
- Sung Ryong Park and Wayne Burleson, ``Reconfiguration for Power Saving in Real-Time Motion Estimation'' (ps file), (slide) ICASSP, May, 1998.
- Michael Petronino, Ray Bambha, James Carswell, Wayne Burleson,
``An FPGA-based Data Acquisition System for a 95 Ghz W-b and Radar'' , 1997 Intl. Conference on Acoustics, Speech and Signal Processing (ICASSP), Munich.
- Bongjin Jung and Wayne Burleson, ``VLSI Array Architectures for Pyramid Vector Quantization'' (abstract), 1996 VLSI Signal Processing Workshop.
- Bongjin Jung and Wayne Burleson,
``Real-Time VLSI Compression for High-Speed Wireless Local Area Networks'' (ps file), 1995 Data Compression Conference.
- Yongjin Jeong and Wayne Burleson,
``High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding''(abstract), ISCAS 95.
- Zheng Zhou and W. Burleson,
`` Equivalence Checking of Datapaths based on Canonical Arithmetic Expressions''(ps file) Design Automation Conference 95.
- Roderic A. Grupen, Chris I. Connolly, Kamal X. Souccar, and Wayne P. Burleson, ``Toward a Path Co-Processor for Automated Vehicle Control," IEEE Symposium on Intelligent Vehicles, Detroit, MI September, 1995.
- Mircea Stan and Wayne P. Burleson, ``Low-Power CMOS Clock Drivers," submitted to TAU Timing Workshop, October 1995.
Older publications of VSPG and Burleson: No links here so send email to
email@example.com to obtain electronic or paper copies.